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1
PRELIMINARY
CY7C09349V CY7C09359V
3.3V 4K/8K x 18 Synchronous Dual-Port Static RAM
Features
* True dual-ported memory cells which allow simultaneous access of the same memory location * Two Flow-Through/Pipelined devices -- 4K x 18 organization (CY7C09349V) -- 8K x 18 organization (CY7C09359V) * Three Modes -- Flow-Through -- Pipelined -- Burst * Pipelined output mode on both ports allows fast 83-MHz operation * 0.35-micron CMOS for optimum speed/power
v
* High-speed clock to data access 7.5[1, 2]/9/12 ns (max.) * 3.3V Low operating power -- Active = 135 mA (typical) -- Standby = 10 A (typical) * Fully synchronous interface for easier operation * Burst counters increment addresses internally -- Shorten cycle times -- Minimize bus noise * * * * * -- Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Upper and lower byte controls for bus matching Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP
Logic Block Diagram
R/WL UBL R/WR UBR
CE0L CE1L LBL OEL
1
0/1
1
0/1
0
0
CE0R CE1R LBR OER
FT/PipeL
9
0/1
1b 0b 1a 0a
b a
0a 1a 0b 1b
a b
0/1
FT/PipeR
9
I/O 9L-I/O 17L
9
I/O9R-I/O17R I/O Control I/O Control
9
I/O 0L-I/O 8L A0L-A11/12L CLK L ADSL CNTEN L CNTRST L
[3]
I/O0R-I/O 8R
12/13 12/13
Counter/ Address Register Decode
True Dual-Ported RAM Array
Counter/ Address Register Decode
A0R-A11/12R CLKR ADSR CNTENR CNTRSTR
[3]
Notes: 1. Call for availability 2. See Page 6 for Load Conditions. 3. A0-A11 for 4K; A0-A12 for 8K devices.
For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 October 14, 1999
PRELIMINARY
Functional Description
The CY7C09349V and CY7C09359V are high-speed 3.3V synchronous CMOS 4K and 8K x 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[4] Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 7.5 ns[1] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flowthrough mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times.
CY7C09349V CY7C09359V
A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.
Note: 4. When simultaneously writing to the same location, final value cannot be guaranteed.
2
PRELIMINARY
Pin Configuration
100-Pin TQFP (Top View)
CNTENR CNTENL ADSR CLKR ADSL CLKL
CY7C09349V CY7C09359V
GND
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L [Note 5] A12L NC NC NC LBL UBL CE0L CE1L CNTRSTL R/WL OEL VCC FT/PIPEL I/O17L I/O16L GND I/O15L I/O14L I/O13L 1/012L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 A8R A9R A10R A11R A12R [Note 5] NC NC NC LBR UBR CE0R CE1R CNTRSTR R/WR GND OER FT/PIPER I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R
CY7C09359V (8K x 18) CY7C09349V (4K x 18)
A7R 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/10R
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L I/O3L
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O2L
A0L
I/O1L
I/O0L
I/O0R
I/01R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
Selection Guide
CY7C09349V CY7C09359V -7[1, 2] fMAX2 (MHz) (Pipelined) Max Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current ICC (mA) Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) Typical Standby Current for ISB3 (A) Shaded areas contain advance information.
Note: 5. This pin is NC for CY7C09349V.
CY7C09349V CY7C09359V -9 67 9 135 20 10 A
I/O9R
VCC
GND
GND
VCC
CY7C09349V CY7C09359V -12 50 12 115 20 10 A
83 7.5 155 25 10 A (Both Ports CMOS Level)
3
PRELIMINARY
Pin Definitions
Left Port A0L-A12L ADSL Right Port A0R-A12R ADSR Description Address Inputs (A0-A11 for 4K, A0-A12 for 8K devices).
CY7C09349V CY7C09359V
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during normal read or write transactions. Asserting this signal LOW also loads the burst address counter with data present on the I/O pins. Chip Enable Input. To select either the left or right port, both CE0 AND CE 1 must be asserted to their active states (CE0 V IL and CE1 VIH). Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data Bus Input/Output (I/O0-I/O15 for x16 devices). Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte (I/O0-I/O 8 for x18, I/O0-I/O7 for x16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L-I/O15/17L). Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Ground Input. No Connect. Power Input. Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V Latch-Up Current ..................................................... >200 mA
CE0L,CE1L CLKL CNTENL
CE0R,CE1R CLKR CNTENR
CNTRSTL I/O0L-I/O 17L LBL
CNTRSTR I/O0R-I/O17R LBR
UBL OEL R/WL FT/PIPEL GND NC VCC
UBR OER R/WR FT/PIPE R
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied .............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ...........................-0.5V to VCC+0.5V DC Input Voltage......................................-0.5V to VCC+0.5V
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 300 mV 3.3V 300 mV
Shaded areas contain advance information.
4
PRELIMINARY
Electrical Characteristics Over the Operating Range
CY7C09349V CY7C09359V -7[1, 2] Parameter VOH VOL VIH VIL IOZ ICC ISB1 ISB2 ISB3 ISB4 Description Output HIGH Voltage (VCC = Min., IOH = -4.0 mA) Output LOW Voltage (VCC = Min., IOH = +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Standby Current (Both Ports TTL Level)[6] CEL & CER VIH, f =fMAX Com'l. Indust. Com'l. Indust. 105 10 95 165 250 125 25 85 -10 155 2.0 0.8 10 275 -10 135 185 20 35 95 106 10 10 85 95 2.4 0.4 2.0 0.8 10 230 300 75 85 155 165 250 250 115 125 2.4 0.4 -9
CY7C09349V CY7C09359V
-12 2.4 0.4 2.0 0.8 -10 115 155 20 30 85 95 10 10 75 85 10 180 250 70 80 140 150 250 250 100 110 V V V V A mA mA mA mA mA mA A A mA mA
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Standby Current (One Port TTL Level)[6] Com'l. CEL | CER VIH, f =fMAX Indust. Standby Current (Both Ports CMOS Com'l. Level)[6] CEL & CER VCC - 0.2V, f = 0 Indust. Standby Current (One Port CMOS Level)[6] CEL | CER VIH, f = fMAX Com'l. Indust.
Shaded areas contain advance information.
Capacitance
Parameter CIN Description Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 10 Unit pF
COUT Output Capacitance 10 pF Note: 6. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH).
5
PRELIMINARY
AC Test Loads
3.3V
CY7C09349V CY7C09359V
3.3V R1 = 590 OUTPUT C = 30 pF R2 = 435 VTH = 1.4V OUTPUT C = 30 pF RTH = 250 R1 = 590 OUTPUT C = 5 pF R2 = 435
(a) Normal Load (Load 1)
(b) Thevenin Equivalent (Load 1)
(c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig)
AC Test Loads (Applicable to -7 only)[7]
OUTPUT C
Z0 = 50
R = 50 3.0V GND VTH = 1.4V 10% 3 ns
ALL INPUT PULSES
90% 90% 10% 3 ns
(a) Load 1 (-7 only)
1 .00
0.90
0.80
(ns) for all -7 access times
0.70
0.60
0.50
0.40
0.30
0.20
0.1 0
0.00 10 15 20 25 30 35
Capacitance (pF)
(b) Load Derating Curve
Note: 7. Test Conditions: C = 10 pF.
6
PRELIMINARY
Switching Characteristics Over the Operating Range
CY7C09349V CY7C09359V -7[1, 2] Parameter fMAX1 fMAX2 tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ tCWDD tCCS fMax Pipelined Clock Cycle Time - Flow-Through Clock Cycle Time - Pipelined Clock HIGH Time - Flow-Through Clock LOW Time - Flow-Through Clock HIGH Time - Pipelined Clock LOW Time - Pipelined Clock Rise Time Clock Fall Time Address Set-up Time Address Hold Time Chip Enable Set-up Time Chip Enable Hold Time R/W Set-up Time R/W Hold Time Input Data Set-up Time Input Data Hold Time ADS Set-up Time ADS Hold Time CNTEN Set-up Time CNTEN Hold Time CNTRST Set-up Time CNTRST Hold Time Output Enable to Data Valid OE to Low Z OE to High Z Clock to Data Valid - Flow-Through Clock to Data Valid - Pipelined Data Output Hold After Clock HIGH Clock HIGH to Output High Z Clock HIGH to Output Low Z 2 2 2 9 2 1 7 18 7.5 2 2 2 9 4 0 4 0 4 0 4 0 4 0 4 0 4 0 9 2 1 7 20 9 2 2 2 22 12 7.5 7.5 5 5 3 3 4 1 4 1 4 1 4 1 4 1 4 1 4 1 10 2 1 Description fMax Flow-Through Min. Max. 45 83 25 15 12 12 6 6 3 3 4 1 4 1 4 1 4 1 4 1 4 1 4 1 Min. -9 Max. 40 67 30 20 12 12 8 8
CY7C09349V CY7C09359V
-12 Min. Max. 33 50 Unit MHz MHz ns ns ns ns ns ns 3 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 7 25 12 9 ns ns ns ns ns ns ns ns
Port to Port Delays Write Port Clock HIGH to Read Data Delay Clock to Clock Set-up Time 35 10 40 15 40 15 ns ns
Shaded areas contain advance information.
7
PRELIMINARY
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = V IL)[8, 9, 10, 11]
tCH1 CLK tCYC1 tCL1
CY7C09349V CY7C09359V
CE0 tSC CE1 tHC tSC tHC
R/W tSW tSA ADDRESS DATAOUT tCKLZ tOHZ OE tOE tOLZ An tCD1 tHW tHA An+1 tDC Qn Qn+1 An+2 An+3 tCKHZ Qn+2 tDC
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[8, 9, 10, 11]
tCH2 CLK tCYC2 tCL2
CE0 tSC CE1 tHC tSC tHC
R/W tSW tSA ADDRESS DATAOUT An 1 Latency tHW tHA An+1 tCD2 Qn tCKLZ OE
tOE Notes: 8. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 9. ADS = VIL, CNTEN and CNTRST = VIH. 10. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock. 11. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
An+2 tDC Qn+1 tOHZ
An+3
Qn+2 tOLZ
8
PRELIMINARY
Switching Waveforms (continued)
Bank Select Pipelined Read[12, 13]
tCH2 CLKL tSA ADDRESS(B1) tSC CE0(B1) tCD2 DATAOUT(B1) tSA ADDRESS(B2) A0 tHA A1 tSC CE0(B2) tSC DATAOUT(B2) tCKLZ tHC tCD2 D2 tCKHZ tSC D0 tDC A2 tHC tHC tCD2 D1 tDC A3 A4 tCKLZ tCKHZ tCD2 A0 tHC tHA A1 A2 A3 A4 tCYC2 tCL2
CY7C09349V CY7C09359V
A5
tCKHZ D3
A5
tCD2 D4 tCKLZ
Left Port Write to Flow-Through Right Port Read[14, 15, 16, 17]
CLKL tSW R/WL tSA ADDRESSL tSD DATAINL CLKR R/WR ADDRESSR tSW tSA tHW tHA NO MATCH tCWDD DATAOUTR tDC VALID tDC tCD1 VALID VALID tCCS tCD1 MATCH tHD tHA NO MATCH tHW
MATCH
Notes: 12. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2. Each Bank consists of one Cypress dual-port device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 13. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 14. The same waveforms apply for a right port write to flow-through left port read. 15. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 16. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to. 17. It t CCS maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1. t CWDD does not apply in this case.
9
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = VIL)[11, 18, 19, 20]
tCH2 CLK tCYC2 tCL2
CY7C09349V CY7C09359V
CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN An tHA tCD2 Qn READ NO OPERATION WRITE READ tCKHZ tHW An+1 An+2 An+2 tSD tHD Dn+2 tCKLZ tCD2 Qn+3 An+3 An+4 tHW tHC
DATAOUT
Pipelined Read-to-Write-to-Read (OE Controlled)[11, 18, 19, 20]
tCH2 CLK tCYC2 tCL2
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW An
tHW An+1 tHA An+2 tSD tHD Dn+2 tCD2 Dn+3 tCKLZ Qn tOHZ tCD2 Qn+4 An+3 An+4 An+5
ADDRESS tSA DATAOUT
DATAIN
OE READ WRITE READ
Notes: 18. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. 19. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 20. During "No operation," data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
10
PRELIMINARY
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = VIL)[9, 11, 19, 20]
tCH1 CLK tCYC1 tCL1
CY7C09349V CY7C09359V
CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN tCD1 Qn tDC READ An tHA tCD1 Qn+1 tCKHZ NO OPERATION tCKLZ WRITE tHW An+1 An+2 tSD Dn+2 tCD1 Qn+3 tDC READ tCD1 An+2 tHD An+3 An+4 tHW tHC
DATAOUT
Flow-Through Read-to-Write-to-Read (OE Controlled)[9, 11, 18, 19, 20]
tCH1 CLK tCYC1 tCL1
CE0 tSC CE1 tSW R/W tSW An ADDRESS tSA DATAIN tCD1 Qn tOHZ tCKLZ tHA tDC tSD Dn+2 tHD Dn+3 tOE tCD1 Qn+4 tDC tCD1 tHW An+1 An+2 An+3 An+4 An+5 tHW tHC
DATAOUT
OE READ WRITE READ
11
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance[21]
tCYC2 tCL2
CY7C09349V CY7C09359V
tCH2 CLK tSA ADDRESS tSAD ADS An
tHA
tHAD
tSAD CNTEN tSCN DATAOUT Qx-1 READ EXTERNAL ADDRESS tHCN Qx tDC READ WITH COUNTER tCD2 Qn tSCN Qn+1
tHAD
tHCN Qn+2 Qn+3
COUNTER HOLD
READ WITH COUNTER
Flow-Through Read with Address Counter Advance[21]
tCYC1 tCL1
tCH1 CLK tSA ADDRESS tSAD ADS An
tHA
tHAD tSAD tHAD
CNTEN tSCN tHCN tCD1 Qx tDC READ EXTERNAL ADDRESS Qn Qn+1 tSCN tHCN
DATAOUT
Qn+2 READ WITH COUNTER
Qn+3
READ WITH COUNTER
COUNTER HOLD
Note: 21. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH.
12
PRELIMINARY
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[22, 23]
tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2
CY7C09349V CY7C09359V
INTERNAL ADDRESS tSAD ADS tHAD
An
An+1
An+2
An+3
An+4
CNTEN tSCN DATAIN tSD Dn tHD WRITE EXTERNAL ADDRESS tHCN Dn+1 WRITE WITH COUNTER Dn+1 Dn+2 Dn+3 Dn+4
WRITE COUNTER HOLD
WRITE WITH COUNTER
Notes: 22. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 23. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
13
PRELIMINARY
Switching Waveforms (continued)
Counter Reset (Pipelined Outputs)[11, 18, 24, 25]
tCYC2 tCL2
CY7C09349V CY7C09359V
tCH2 CLK
tSA ADDRESS INTERNAL ADDRESS AX tSW tHW 0 1 An
tHA An+1 An An+1
R/W tSAD ADS tSCN CNTEN tSRST CNTRST DATAIN tHRST tSD D0 Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Q1 READ ADDRESS n Qn tHD tHCN tHAD
DATAOUT
Notes: 24. CE0, UB, and LB = VIL; CE1 = VIH. 25. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
14
PRELIMINARY
Read/Write and Enable Operation[26, 27, 28]
Inputs OE X X X L H X CLK CE0 H X L L L CE1 X L H H H R/W X X L H X Outputs I/O0-I/O17 High-Z High-Z DIN DOUT High-Z Deselected
CY7C09349V CY7C09359V
Operation
[29]
Deselected[29] Write Read[29] Outputs Disabled
Address Counter Control Operation[26, 30, 31, 32]
Address X An X X Previous Address X X An An CLK ADS X L H H CNTEN X X H L CNTRST L H H H I/O Dout(0) Dout(n) Dout(n) Dout(n+1) Mode Reset Load Hold Increment Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked--Counter Disabled Counter Enabled--Internal Address Generation
Notes: 26. "X" = "don't care," "H" = VIH, "L" = VIL. 27. ADS, CNTEN, CNTRST = "don't care." 28. OE is an asynchronous input signal. 29. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle. 30. CE0 and OE = VIL; CE1 and R/W = VIH. 31. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 32. Counter operation is independent of CE0 and CE1.
15
PRELIMINARY
Ordering Information
4K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) 7.5[1, 2] 9 12 Ordering Code CY7C09349V-7AC CY7C09349V-9AC CY7C09349V-9AI CY7C09349V-12AC CY7C09349V-12AI 8K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) 7.5[1, 2] 9 12 Ordering Code CY7C09359V-7AC CY7C09359V-9AC CY7C09359V-9AI CY7C09359V-12AC CY7C09359V-12AI
Shaded areas contain advance information.
CY7C09349V CY7C09359V
Package Name A100 A100 A100 A100 A100
Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
Operating Range Commercial Commercial Industrial Commercial Industrial
Package Name A100 A100 A100 A100 A100
Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
Operating Range Commercial Commercial Industrial Commercial Industrial
Document #: 38-00676-C
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-A
16
PRELIMINARY
CY7C036 Dual Port Design Consideration - Data Sheet Addendum
This design consideration applies to the Internal Power-OnReset (POR) circuit used on the CY7C036 and its derivatives listed below. Power supply ramp--The devices will function properly and meet all data sheet specifications if the power supply ramp rate is greater than 100 ns. If ramp is less than 100 ns, you may see a non-destructive failure in which the device will not respond to changes in address or clock, but the I/Os will respond to the output enable. Applications consideration--If the power supply ramps in less than 100 ns, a small resistor (20-50), a large capacitor, or an RC network can be connected at the output of the power supply to ground. The addition of a resistor will help clean up the power lines, while the capacitor will slow down the ramp rate
CY7C09349V CY7C09359V
without the loss of any power. Contact your local Cypress FAE for assistance as needed. Troubleshooting--If a problem occurs with the part, power down the device to ground and then power up again at slower ramp rate (greater than 100 ns) in order to confirm that the problem might be due to the POR circuit. If the dual-port functions properly once the ramp rate is slowed to 100 ns or greater, then the POR circuit is at fault. Applicable devices--All speed/package/temperature combinations of the following: * CY7C09349V * CY7C09359V Cypress design change--Cypress design team has identified the root cause. A permanent circuit change and die revision will be available beginning in October and will be identified by the letter "A" in the part number.
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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